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3958
DMOS FULL-BRIDGE PWM MOTOR DRIVER
A3958SLB
CHARGE PUMP
CP CP2 CP1 PHASE OSC GROUND GROUND LOGIC SUPPLY ENABLE DATA CLOCK STROBE
1 2 3 4 5
24 23 NC 22 21 VBB 20 19 18
VREG RANGE NO CONNECTION OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA NO CONNECTION MODE REF
Dwg. PP-069A
Designed for pulse-width modulated (PWM) current control of dc motors, the A3958SB and A3958SLB are capable of continuous output currents to 2 A and operating voltages to 50 V. Internal fixed offtime PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM-control signals. The ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power-up sequencing is not required. The A3958SB/SLB is supplied in a choice of two power packages, a 24-pin plastic DIP with a copper batwing tab (package suffix `B'), and a 24-pin plastic SOIC with a copper batwing tab (package suffix `LB'). In both cases, the power tab is at ground potential and needs no electrical isolation. Each package type is available in a lead-free version (100% matte tin leadframe).
Data Sheet 29319.31D
6 7 8 9 9 V DD
LOGIC
17 16
SERIAL PORT
10 11 12
NC
15 14
/
13
Note that the A3958SLB(SOIC) and A3958SB (DIP) do not share a common terminal assignment.
FEATURES
2 A, 50 V Continuous Output Rating Low rDS(on) Outputs (270 m, Typical) Programmable Mixed, Fast, and Slow Current-Decay Modes Serial Interface Controls Chip Functions Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal-Shutdown Circuitry Crossover-Current Protection
RJA (C/W) 40 40 77 RJT (C/W) 6 6 6
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ...................... 50 V Output Current, IOUT ............................. 2.0 A Logic Supply Voltage, VDD .................... 7.0 V Input Voltage, VIN ....... -0.3 V to VDD + 0.3 V Sense Voltage, VS ................................... 0.5 V Reference Voltage, VREF ........................ 2.7 V Package Power Dissipation (TA = 25C), PD A3958SB ...................................... 3.1 W* A3958SLB .................................... 1.6 W* Operating Temperature Range, TA .................................... -20C to +85C Junction Temperature, TJ .................................................. +150C Storage Temperature Range, TS .................................. -55C to +150C
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. * Per SEMI G42-88 Specification.
Part Number A3958SB-T A3958SLB-T A3958SLBTR-T
*
Pb-free* Yes Yes Yes
Package 16-Pin DIP 16-Lead SOIC 16-Lead SOIC
Packing 25 per Tube 47 per Tube 1000 per reel
Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for receipt of LAST TIME BUY orders: April 27, 2007. These variants include: A3958SB, A3958SLB and A3958SLBTR.
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
VDD LOGIC SUPPLY
CHARGE PUMP BANDGAP VDD CREG TSD
VBB
+
CP1 CP2
LOAD SUPPLY BANDGAP REGULATOR VREG
UNDERVOLTAGE & FAULT DETECT
CHARGE PUMP
CONTROL LOGIC OUTA
PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT
MODE PHASE ENABLE
GATE DRIVE
CP
OUTB SENSE
ZERO CURRENT DETECT
CS RS
OSC
FIXED OFF PROGRAMMABLE BLANK DECAY PWM TIMER
CLOCK DATA STROBE RANGE
SERIAL PORT
SLEEP MODE
CURRENT SENSE
RANGE
REFERENCE BUFFER & DIVIDER
REF
VREF
Dwg. FP-048
CP2 CP1 PHASE OSC GROUND GROUND GROUND GROUND LOGIC SUPPLY ENABLE DATA CLOCK
1 2 3 4 5
CHARGE PUMP
24 23 22 21 VBB 20 19 18 17
CP VREG RANGE OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA MODE REF STROBE
Dwg. PP-069-1A
A3958SB
Note that the A3958SLB (SOIC) and A3958SB (DIP) do not share a common terminal assignment.
6 7 8 9 9 10 11 12 V DD
LOGIC
16 15
/
SERIAL PORT
14 13
2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2000, 2002 Allegro MicroSystems, Inc.
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise)
Limits Characteristics Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Load Supply Current VBB IDSS rDS(on) VF IBB Operating During sleep mode VOUT = VBB VOUT = 0 V Source driver, IOUT = -2 A Sink driver, IOUT = 2 A Source diode, IF = -2 A Sink diode, IF = 2 A fPWM < 50 kHz Charge pump on, outputs disabled Sleep Mode Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current (all inputs except ENABLE) ENABLE Input Current OSC input frequency OSC input duty cycle OSC input hysteresis Input Hysterisis Reference Input Volt. Range Reference Input Current Comparator Input Offset Volt. VDD VIN(1) VIN(0) IIN(1) IIN(0) IIN(1) IIN(0) fOSC dcOSC - - VREF IREF VIO VIN = 2.0 V VIN = 0.8 V VIN = 2.0 V VIN = 0.8 V Operating Operating Operating All digital inputs except OSC Operating VREF = 2.5 V VREF = 0 V Operating 4.5 2.0 - - - - - 2.9 40 200 50 0.0 - - 5.0 - - <1.0 <-2.0 40 16 - - - - - - 0 5.5 - 0.8 20 -20 100 40 6.1 60 400 100 2.6 0.5 5.0 V V V A A A A MHz % mV mV V A mV 20 0 - - - - - - - - - - - <1.0 <-1.0 270 270 1.2 1.2 4.0 2.0 - 50 50 20 -20 300 300 1.6 1.6 7.0 5.0 20 V V A A m m V V mA mA A Symbol Test Conditions Min. Typ. Max. Units
Continued next page ...
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3
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise), continued.
Limits Characteristics Control Logic Buffer Input Offset Volt. Reference Divider Ratio Propagation Delay Times VIO - tpd D14 = High D14 = Low PWM change to source ON PWM change to source OFF PWM change to sink ON PWM change to sink OFF Phase change to sink ON Phase change to sink OFF Phase change to source ON Phase change to source OFF Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current TJ TJ UVLO UVLO IDD fPWM < 50 kHz Sleep Mode, Inputs < 0.5 V Increasing VDD - 9.9 4.95 - - - - - - - - - - 3.90 0.05 - - 0 10 5.0 600 100 600 100 600 100 600 100 165 15 4.2 0.10 6.0 - 15 10.2 5.05 - - - - - - - - - - 4.45 - 10 2.0 mV - - ns ns ns ns ns ns ns ns C C V V mA mA Symbol Test Conditions Min. Typ. Max. Units
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
Serial Interface. The A3958 is controlled via a 3-wire (clock, data, strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is clocked in starting with D19. Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Function Blank Time LSB Blank Time MSB Off Time LSB Off Time Bit 1 Off Time Bit 2 Off Time Bit 3 Off Time MSB Fast Decay Time LSB Fast Decay Time Bit 1 Fast Decay Time Bit 2 Fast Decay Time MSB Sync. Rect. Mode Sync. Rect. Enable External PWM Mode Enable Phase Reference Range Select Internal PWM Mode Test Use Only Sleep Mode D7 - D10 Fast Decay Time. A four-bit word sets the fast-decay portion of the fixed-off time for the internal PWM control circuitry. This will only have impact if the mixed-decay mode is selected (via bit D17 and the MODE input terminal). For tfd > toff, the device will effectively operate in the fast-decay mode. The fast decay portion is defined by tfd = (8[1 + N]/fosc) - 1/fosc where N = 0 ... 15 For example, with an oscillator frequency of 4 MHz, the fast decay time will be adjustable from 1.75 s to 31.75 s in increments of 2 s. D11 Synchronous Rectification Mode. The active mode prevents reversal of load current by turning off synchronous rectification when a zero current level is detected. The passive mode will allow reversal of current but will turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by VREF/RS. D11 0 1 Mode Active Passive
D12 Synchronous Rectification Enable. D12 0 1 Synchronous Rect. Disabled Enabled
D0 - D1 Blank Time. The current-sense comparator is blanked when any output driver is switched on, according to the table below. fosc is the oscillator input frequency. D1 0 0 1 1 D0 0 1 0 1 Blank Time 4/fosc 6/fosc 12/fosc 24/fosc
D13 External PWM Decay Mode. Bit D13 determines the current-decay mode when using ENABLE chopping for external PWM current control. D13 0 1 Mode Fast Slow
D2 - D6 Fixed-Off Time. A five-bit word sets the fixed-off time for internal PWM current control. The off time is defined by toff = (8[1 + N]/fosc) - 1/fosc where N = 0 ... 31 For example, with an oscillator frequency of 4 MHz, the off time will be adjustable from 1.75 s to 63.75 s in increments of 2 s.
D14 Enable Logic. Bit D14, in conjunction with ENABLE, determines if the output drivers are in the chopped (OFF)(ENABLE = D14) or ON (ENABLE D14) state. ENABLE 0 1 0 1 D14 0 0 1 1 Mode Chopped On On Chopped
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3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
D15 Phase Logic. Bit D15, in conjunction with PHASE, determines if the device is operating in the forward (PHASE D15) or reverse (PHASE = D15) state. PHASE D15 State 0 0 Reverse 1 0 Forward 0 1 Forward 1 1 Reverse OUTA OUTB Low High High Low High Low Low High D18 Test Mode. Bit D18 low (default) operates the device in normal mode. D18 is only used for testing purposes. The user should never change this bit. D19 Sleep Mode. Bit D19 selects a Sleep mode to minimize power consumption when not in use. This disables much of the internal circuitry including the regulator and charge pump. On power up the serial port is initialized to all 0s. Bit D19 should be programmed high for 1 ms before attempting to enable any output driver. D19 0 1 Sleep Mode Sleep Normal
D16 Gm Range Select. Bit D16, in conjunction with RANGE, determines if VREF is divided by 5 (RANGE D16) or by 10 (RANGE = D16). RANGE 0 1 0 1 D16 0 0 1 1 Divider /10 /5 /5 /10
D17 Internal PWM Mode. Bit D17, in conjunction with MODE, selects slow (MODE D17) or mixed (MODE = D17) current decay. MODE D17 0 0 1 0 0 1 1 1 Current-Decay Mode Mixed Slow Slow Mixed
Serial Port Write Timing Operation. Data is clocked into the shift register on the rising edge of the CLOCK signal. Normally STROBE will be held high, only brought low to initiate a write cycle. Refer to diagram below and these specifications for the minimum timing requirements. A.DATA setup time ......................................... 15 ns B.DATA hold time ........................................... 10 ns C.Setup STROBE to CLOCK rising edge ....... 50 ns D.CLOCK high pulse width ............................ 50 ns E.CLOCK low pulse width .............................. 50 ns F.Setup CLOCK rising edge to STROBE ....... 50 ns G.STROBE pulse width ................................... 50 ns
Serial Port Write Timing
STROBE C CLOCK A DATA D19 B D18 D0 D E F G
Dwg. WP-038
6
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 F capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The charge pump is used to generate a gate-supply voltage greater than VBB to drive the sourceside DMOS gates. A 0.22 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 F ceramic capacitor should be connected between CP and VBB to act as a reservoir to operate the high-side DMOS devices. The CP voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on CP or VREG) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers and resets the data in the serial port to all zeros. PWM Timer Function. The PWM timer is programmable via the serial port (bits D2 - D10) to provide off-time PWM signals to the control circuitry. In the mixed current-decay mode, the first portion of the off time operates in fast decay, until the fast decay time count (serial bits D7 - D10) is reached, followed by slow decay for the rest of the off-time period (bits D2 - D6). If the fast decay time is set longer than the off time, the device effectively operates in fast decay mode. Bit D17, in conjunction with MODE, selects mixed or slow decay. PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter (see bits D2 - D6) to provide the programmable blanking function. The blank timer is reset when ENABLE is chopped or PHASE is changed. For external PWM control, a PHASE change or ENABLE on will trigger the blanking function. Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3958 synchronous rectification feature will turn on the opposite pair of DMOS outputs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification can be configured in active mode, passive mode, or disabled via the serial port (bits D11 and D12). The active or passive mode selection has no impact in slow-decay mode. With synchronous rectification enabled, the slow-decay mode serves as an effective brake mode. Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS), the applied analog reference voltage (VREF), the RANGE logic level, and serial data bit D16: When RANGE = D16 ........... ITRIP = VREF/10RS When RANGE D16 ............ ITRIP = VREF/5RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the serial-port-programmed fixed off-time period. The current path during recirculation is determined by the configuration of slow/mixed current-decay mode (D17) and the synchronous rectification control bits (D11 and D12).
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3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
APPLICATIONS INFORMATION
Current Sensing. To minimize inaccuracies in sensing the ITRIP current level, which may be caused by ground trace IR drops, the sense resistor should have an independent ground return to the ground terminal of the device. For low-value sense resistors the IR drops in the PCB sense resistor's traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. The maximum value of RS is given as RS 0.5/ITRIP. Braking. The braking function is implemented by driving the device in slow-decay mode via serial port bit D13, enabling synchronous rectification via bit D12, and chopping with the combination of D14 and the ENABLE input terminal. Because it is possible to drive current in either direction through the DMOS drivers, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. It is important to note that the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by VBEMF/ RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance*, the driver should be soldered directly onto the board. The ground side of RS should have an individual path to the ground terminals of the device. This path should be as short as is possible physically and should not have any other components connected to it. It is recommended that a 0.1 F capacitor be placed between SENSE and ground as close to the device as possible; the load supply terminal, VBB, should be decoupled with an electrolytic capacitor (> 47 F is recommended) placed as close to the device as is possible. * The thermal resistance and absolute maximum allowable package power dissipation specified on page 1 is measured on typical two-sided PCB with minimal copper ground area. See also, Application Note 29501.5, Improving Batwing Power Dissipation. For example, for the `LB' package (SOIC), RJA can be reduced to 49C/W with 3.57 in2 copper ground area
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
5
RJT = 6.0C/W
4
3
SUFFIX 'B', R JA = 40C/W
2
1
SUFFIX 'LB', R JA = 77C/W
0 25 50 75 100 TEMPERATURE IN C 125 150
Dwg. GP-049B
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
Terminal List A3958SLB (SOIC)
1 2&3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18, 19 20 21 22 23 24
Terminal Name
CP CP1 & CP2 PHASE OSC GROUND LOGIC SUPPLY ENABLE DATA CLOCK STROBE REF MODE NO CONNECT OUTA SENSE GROUND LOAD SUPPLY OUTB NO CONNECT RANGE VREG
Terminal Description
Reservoir capacitor (typically 0.22 F) The charge pump capacitor (typically 0.22 F) Logic input for direction control (see also D15) Logic-level oscillator (square wave) input Grounds VDD, the low voltage (typically 5 V) supply Logic input for enable control (see also D14) Logic-level input for serial interface Logic input for serial port (data is entered on rising edge) Logic input for serial port (active on rising edge) VREF, the load current reference input volt. (see also D16) Logic input for PWM mode control (see also D17) No (Internal) Connection One of two DMOS bridge outputs to the motor Sense resistor Grounds VBB, the high-current, 20 V to 50 V, motor supply One of two DMOS bridge outputs to the motor No (Internal) connection Logic Input for VREF range control (see also D16) Regulator decoupling capacitor (typically 0.22 F)
A3958SB (DIP)
24 1&2 3 4 5, 6, 7, 8* 9 10 11 12 13 14 15 -- 16 17 18, 19* 20 21 -- 22 23
* For the A3958SB DIP only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally.
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3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
A3958SB
Dimensions in Inches (controlling dimensions)
0.014 0.008
24
NOTE 1
13
0.430 0.280 0.240
MAX
0.300
BSC
1
0.070 0.045
6
7 1.280 1.230
0.100
BSC
12
0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-25A in
Dimensions in Millimeters (for reference only)
24
NOTE 1
13
0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1
1.77 1.15
6
7 32.51 31.24
2.54
BSC
12
0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-25A mm
NOTES: 1. 2. 3. 4. 5.
Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 15 devices.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
A3958SLB
Dimensions in Inches (for reference only)
24 13
0.0125 0.0091
0.2992 0.2914
0.419 0.394 0.050 0.016
0.020 0.013
1
2
3
0.6141 0.5985
0.050
BSC NOTE 1 NOTE 3
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-25A in
Dimensions in Millimeters (controlling dimensions)
24 13
0.32 0.23
7.60 7.40
10.65 10.00 1.27 0.40
0.51 0.33
1
2
3
15.60 15.20
1.27
BSC NOTE 1 NOTE 3
0 TO 8
2.65 2.35 0.10 MIN.
NOTES: 1. 2. 3. 4.
Dwg. MA-008-25A mm
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Supplied in standard sticks/tubes of 31 devices or add "TR" to part number for tape and reel.
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3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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